System Level Simulation of Digital Designs: a Case Study

.............................................................................................................................. I TABLE OF CONTENTS............................................................................................................ I LIST OF FIGURES................................................................................................................. IV LIST OF TABLES.....................................................................................................................V ACKNOWLEDGMENTS ....................................................................................................... VI NOMENCLATURE ...............................................................................................................VII CHAPTER 1:INTRODUCTION .............................................................................................. 1 1.1 THESIS OUTLINE............................................................................................................. 2 CHAPTER 2:VIRTUAL PROTOTYPING .............................................................................. 5 2.1 RAPID APPLICATION SPECIFIC SIGNAL-PROCESSOR PROTOTYPING (RASSP)....................... 5 2.2 BENEFITS OF VIRTUAL PROTOTYPING .............................................................................. 6 2.3 VHDL........................................................................................................................... 7 2.3.1 The History of VHDL ............................................................................................ 7 2.3.2 VHDL Standards .................................................................................................. 7 2.3.3 VHDL Software .................................................................................................... 7 2.4 VHDL CODING .............................................................................................................. 9 2.5 VHDL MODELLING.......................................................................................................10 2.5.1 Temporal Resolution............................................................................................11 2.5.2 Data Resolution...................................................................................................11 2.5.3 Functional Resolution ..........................................................................................11 2.5.4 Structural Resolution ...........................................................................................12 2.5.5 Software Programming Resolution .......................................................................12 2.6 GENERAL MODELLING STYLES.......................................................................................12 2.6.1 Behavioural Model ..............................................................................................12 2.6.2 Functional Model ................................................................................................12 2.6.3 Structural Model..................................................................................................12 2.7 SYSTEM MODELS ..........................................................................................................13 2.7.1 Executable Specification ......................................................................................13 2.7.2 Mathematical Model ............................................................................................13 2.7.3 Algorithm Model..................................................................................................13 2.8 LOCATION OF MODELS ..................................................................................................14 CHAPTER 3:FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)..................................16 3.1 WHAT IS AN FPGA? ......................................................................................................16 3.1.1 The Logic Cells....................................................................................................17 3.1.2 The I/O Cells .......................................................................................................18 3.1.3 The Interconnect Matrix .......................................................................................19 3.2 PRODUCING AN FPGA DESIGN .......................................................................................19 3.2.1 Design Entry .......................................................................................................19 3.2.2 Logic synthesis ....................................................................................................20 3.2.3 Place-and-route...................................................................................................20 3.2.4 Programming the FPGA ......................................................................................21 3.3 DIGITAL SIGNAL PROCESSING IN FPGAS.........................................................................21